1. Field of the Invention
The present invention generally relates to a semiconductor package structure. More particularly, the present invention relates to a substrate on chip (SOC) package structure.
2. Description of Related Art
The so-called “SOC (Substrate-On-Chip) packaging” refers to a common semiconductor packaging structure. In such structure, semiconductor chips are attached on a substrate with holes, and a plurality of metal bonding wires connect the substrate with the chips via the holes. Normally the substrate is also formed with a plurality of solder balls in a grid array. In the U.S. Pat. No. 6,190,943 entitled “CHIP SCALE PACKAGING METHOD”, a chip scale package structure and a packaging method are disclosed. As shown in FIG. 1, the chip scale package 20 comprises a wiring substrate 22, a semiconductor chip 24, and a plurality of spherical bonding balls 44. The substrate 22 has an upper surface 30 for attaching the chip 24 and an underside 38 with the spherical bonding balls 44 implanted therein, and through holes 34 passing through the upper surface 30 and the underside 38. The chip 24 is attached to the upper surface 30 of the substrate 22 by a thermoplastic adhesive layer 28. The through holes 34 of substrate 22 expose the bonding pads 36 of the active surface 26 on chip 24 so that the bonding wires 32 may connect the bonding pads 36 of the chip 24 and the conductive area 41 of substrate 22 via the through holes 34. The conductive area 41 is provided with a conductive layer 40 formed on the underside 38 of substrate 22. The fringe of the chip 24, and each of the through holes 34 of substrate 22 are protected by a passivation layer 42 of a non-conducting resin material.
As shown in FIG. 2, the method for making the chip scale package structure 20 disclosed in the U.S. Pat. No. 6,190,943 entitled “CHIP SCALE PACKAGING METHOD” comprises the steps of: (a) providing a substrate 22 with an upper surface 30 which is provided with at least one chip-implanting area 302 including the through holes 34 mentioned above; (b) coating a thermoplastic adhesive layer 28 on the chip-implanting areas 302 by stenciling; (c) implanting chips 24 in the area 302 such that the active surfaces 26 are in contact with the thermoplastic adhesive layer 28, and that the bonding pads 36 are corresponding in location to the through holes 34; (d) heating the substrate 22 and the chips 24 under pressure for a predetermined period of time; (e) forming the bonding wires 32 connecting the conductive area 41 of the substrate 22 with the bonding pads 36 of the chips 24 by wire-bonding via the through holes 34; (f) providing a passivation layer 42 on the fringe of the chip 24 and the through holes 34; and (g) implanting a plurality of bonding balls 44 in a grid array on the underside 38 of the substrate 22. The chip scale package structure 20 is therefore formed by following the above-mentioned steps.
However, the chip scale package structure 20 has the following disadvantages:    1. The thermoplastic adhesive layer 28 mentioned in step (b) is an elastic, semi-liquid, solvent-free thermoplastic silicon rubber. Because it is semi-liquid before attachment, during the heating and pressuring process, the thermoplastic adhesive layer 28 in step (d) is easy to overflow and thus cover the bonding pads 36 of the chip 24, causing packaging failure.    2. After the thermoplastic adhesive layer 28 is coated in step (b), the substrates 22 cannot be piled up for delivery or storage. The thermoplastic adhesive layer 28 must be attached to the chips 24 as soon as possible, otherwise, the substrates 22 will be contaminated and adhere to each other, causing difficulties in the manufacture process.    3. With the increase of the operation frequency of the chip 24, the heat generated from the chip 24 also increases, such that the heat dissipation of the chip scale package structure 20 becomes more and more important.